In PLL circuits the phases of two signals are synchronized with each other in a closed control loop. Conventional circuits of this type are constructed in the manner indicated in FIG. 1. A voltage controlled oscillator (VCO) issues an output signal which, on the one hand, is present as the output signal at an output terminal VCO.sub.OUT and which, on the other hand, is supplied to an input of a phase comparator PC. A reference signal, with the frequency and phase of which the voltage controlled oscillator VCO is to be synchronized, is supplied to a second input PC.sub.IN of the phase comparator PC. The output of the phase comparator PC is followed by a RC low pass filter circuit whose output signal, which is dependent upon the phase comparison in the phase comparator PC, is supplied to the voltage controlled oscillator VCO as a control signal.
A PLL circuit of the type indicated at the beginning, which is known for U.S. Pat. No. 3,714,463, comprises a phase comparator having two output terminals controlling one current source each. Depending on whether the phase of the output signal of the voltage controlled oscillator is equal to the phase of the reference signal, is leading in respect of the latter or lagging in respect of the latter, the capacitor belonging to a RC low pass filter circuit is held at a mean voltage value or is charged or discharged further in a pulse-like manner by opening in a pulse-like manner the one or the other current source respectively. Such a PLL circuit is also shown in the Patents Abstracts of Japan, No. 55-10238(A).
Due to the fact that the RC low pass filter circuit has to have a large time constant, a capacitor C with large capacitance and a resistor R with large resistance are required in general. Especially the necessity of a capacitor C with large capacitance makes it more difficult to accommodate the low pass filter circuit in a monolithic integrated circuit. A very large semiconductor chip area would be needed for such a capacitor.